The general description of AD9912 says that the PPL allows clocks as low as 25MHz. But later on in the AC specifications the input frequency range with SYSCLK PLL doubler are specifyed to: 6 to 100 MHz?
I would like to use a 10MHz reference clock, enable the clock doubler, divide the sampling clock by fixed 2 and divide by N=24 giving me a DAC sampling clock on 960MHz. would this work?
Also the datasheet says in the SYSCLK PLL doubler section “When employing the doubler, care must be taken to ensure that the loop bandwidth of the SYSCLK PLL multiplier adequately suppresses the sub harmonic. “ So how to realize a optimal PLL loop filter?
University of Aarhus
Department of Physics & Astronomy