Hello,

I'm having trouble understanding the limitations on SCLK when my SPORT is the receive master. The hardware reference manual (HRM Rev 0.3, page 10-9) and the response to another questions in this forum (http://ez.analog.com/message/9830) both quote these formulas:

1) Transmit master: SCLK = PCLK ÷ (4(CLKDIV + 1))

2) Receive master: SCLK = PCLK ÷ (8(CLKDIV + 1))

3) CLKDIV = (PCLK ÷ (4 × SCLK)) – 1 ---> **Note that the HRM is missing the brackets around the "4 x SCLK"**

**Question #1:**

If the formula for Receive master is different than for transmit master, why isn't there a second formula for CLKDIV. For example, CLKDIV = (PCLK ÷ (8 × SCLK)) – 1

**Question #2:**

In my case, CCLK = 260 MHz, PCLK = 130 MHz. I'm trying to run as fast as possible with these clock rates so my CLKDIV is 0 (DIVx = 0x00 << 1). According to formula 2, I would expect to see 16.25 MHz on the scope (130/8(0+1) = 16.25). What I do see is 32.5 MHz. Did I configure something incorrectly or are the forumlas incorrect?

My SPORT configuration is as follows: SPCTLx = LAFS | FSR | ICLK | SLEN8 | LSBF | DTYPE0 | SPEN_A;

**Question #3:**

In the example above, what is the maximum allowable SPORT clock frequency? Is it 32.5 or 16.25 MHz?

Best regards,

Eric

Hi Eric,

>>1) Transmit master: SCLK = PCLK ÷ (4(CLKDIV + 1))

>>2) Receive master: SCLK = PCLK ÷ (8(CLKDIV + 1))

The above formulas are intended to define the maximum SCLK frequency based on the mode whether it is a transmit master or a receive master. I see where the confusion comes from based on the wording in the HRM. The above formulas are true to determine the maximum SCLK frequency. We will make corrections to the manual to avoid any confusion. To calculate the CLKDIV value you need to use the following formula irrespective of the mode used but ensure that the CLKDIV value is such that you do not exceed the maximum SCLK rate supported for that mode. In case of of slave tranmitter and master receiver the maximum SCLK rate is fpclk/8 which that for master transmitter and slave receiver the maximum SCLK supported is fpclk/4.

CLKDIV = (PCLK ÷ (4 ×SCLK)) – 1Question #1:>>If the formula for Receive master is different than for transmit master, why isn't there a second formula for CLKDIV. For example, CLKDIV = (PCLK ÷ (8 × >>SCLK)) – 1

The formula for all the modes(transmit and receive) to calculate CLKDIV should be as follows.

CLKDIV = (PCLK ÷ (4 × SCLK)) – 1 which translates toSCLK=

PCLK÷ (4(CLKDIV+ 1)) for all modesQuestion #2:>>In my case, CCLK = 260 MHz, PCLK = 130 MHz. I'm trying to run as fast as possible with these clock rates so my CLKDIV is 0 (DIVx = 0x00 << 1). >>According to formula 2, I would expect to see 16.25 MHz on the scope (130/8(0+1) = 16.25). What I do see is 32.5 MHz. Did I configure something >>incorrectly or are the forumlas incorrect?>>My SPORT configuration is as follows: SPCTLx = LAFS | FSR | ICLK | SLEN8 | LSBF | DTYPE0 | SPEN_A;As I mentioned above the formula for all modes is

CLKDIV

= (PCLK÷ (4 ×SCLK)) – 1 therefore SCLK should always beSCLK

=PCLK÷ (4(CLKDIV+ 1))In your case with CLKDIV is 0 you have

SCLK = 130MHz /4 = 32.5Mhz which is what you are seeing.

Question #3:>>In the example above, what is the maximum allowable SPORT clock frequency? Is it 32.5 or 16.25 MHz?

The maximum allowable SPORT clock frequency in your case where the SPORT is configured as receive master it should be fpclk/8 which is 16.25Mhz. For this you should use the CLKDIV value of 1. Note that CLKDIV value must be programmed from bit 1 of the CLKDIV register.

Hope the above clarifes.

Thanks,

Divya