# 21469 Receive Master CLKDIV Calculation

Question asked by ForExample on Jan 25, 2011
Latest reply on Mar 28, 2011 by DivyaS

Hello,

I'm having trouble understanding the limitations on SCLK when my SPORT is the receive master.  The hardware reference manual (HRM Rev 0.3, page 10-9) and the response to another questions in this forum (http://ez.analog.com/message/9830) both quote these formulas:

1) Transmit master: SCLK = PCLK ÷ (4(CLKDIV + 1))
2) Receive master: SCLK = PCLK ÷ (8(CLKDIV + 1))

3) CLKDIV = (PCLK ÷ (4 × SCLK)) – 1  ---> Note that the HRM is missing the brackets around the "4 x SCLK"

Question #1:

If the formula for Receive master is different than for transmit master, why isn't there a second formula for CLKDIV.  For example, CLKDIV = (PCLK ÷ (8 × SCLK)) – 1

Question #2:

In my case, CCLK = 260 MHz, PCLK = 130 MHz.  I'm trying to run as fast as possible with these clock rates so my CLKDIV is 0 (DIVx = 0x00 << 1).  According to formula 2, I would expect to see 16.25 MHz on the scope (130/8(0+1) = 16.25).  What I do see is 32.5 MHz.  Did I configure something incorrectly or are the forumlas incorrect?

My SPORT configuration is as follows:  SPCTLx = LAFS | FSR | ICLK | SLEN8 | LSBF | DTYPE0 | SPEN_A;

Question #3:

In the example above, what is the maximum allowable SPORT clock frequency?  Is it 32.5 or 16.25 MHz?

Best regards,

Eric