What do I have to connect the AD8045 exposed paddle to?
The AD8045 exposed pad or paddle needs to be connected to the -Vs supply. With the AD8045 there is an internal connection to -Vs (the negative supply) and exposed paddle and therefore it must be connected to the same potential as the -Vs pin. This tends to be the exception to the rule and not the norm, so its always best to throughly read the datasheet to find out where the exposed pad or paddle needs to be connected and what other special considerations may be required when using an IC.
Since expose paddle was mention here. We have had a lots on enquiry regarding this, not just specifically on the AD8045.
Regarding ... how (best) in connecting the Expose paddle... “in General”. The Expose Paddle otherwise, sometime Also Known As (AKA) expose pads. Thus I would like to add to this thread and summarize the followings.
(a) These are for thermal relief.
(b) These can be connected to a solder plane or connected to the most negative(PCB) supply plane, (note. they can be in some cases, but not always you need to read the datasheet), see (d) below for more info.
(c) wrt multi layer PCB planes, (for best practice and performance). it is recommended that these ‘required’ planes on all layers under the paddle be stitched together with vias.
(d) Pending on the IC’s Voltages supply/supplies (Vs) and ground (Gnd, i.e. 0v) e.g. ( +Vs and gnd), (+/- Vs and gnd). Connecting these expose pad is ... to the most negative supply plane of the respected IC in question. Connecting to ground is usually the best and easiest case, unless otherwise noted in the datasheet, such as the AD8045.
(i) if an IC has only +Vs and gnd, then the expose pad is connected to the gnd plane such as the AD8352, AD9776A,
(ii) If an IC has +/-Vs and gnd, then the expose pad is connected to the -Vs plane such as the AD8045,
N.B there are some update (exceptions) to this rule-of-thumb, please read threads further down.
(e) Majority of cases, the expose pads are describe well within the respected datasheet/device in question. We recommend user to consult this (as first hand info, from the datasheet). If this is not specified in the datasheet i.e. ADN8831 (rev.0). you can use the above as a general rule-of-thumb. More specifically if you are unsure and if it’s definitely not stated in the datasheet. We highly recommend that you contact us for clarification.
In general the expose pad are internally connected... But not always (repeat not always) see AD7682 (rev.B), if in this case then this can, either be connected to gnd plane or just to a solder plane which act as a heat sink.
So, connecting the Expose paddle or (Expose pads) ... The bottom line is, IC specific, pending on supply or supplies.
More ref/info can be obtained via Analog website
(1) MT-093, Thermal Design Basics
(2) App note, AN-772, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP)
I heartedly agree with Ching and John that the paddle connection is IC dependent. Please read the datasheet carefully regarding how to connect the paddle. The paddle is often connected to the substrate of the part, whose bias voltage depends on the architecture of the part. If you connect a different voltage to substrate connected paddle (say by connecting ground when it was supposed to be -Vs), then you can short out your supply.
As an example of a product that breaks most of the rules of thumb, I'll point out the AD8224 which comes in an LFCSP with an exposed paddle. The AD8224 has a substrate biased at the positive supply, so if the paddle is connected, it needs to be connected to +Vs. It is typically best practice to solder to the paddle both for thermal dissipation as well as vibration robustness. However the AD8224 is a low power part in a fairly small package. So it is not necessary to connect to the paddle on the AD8224.
Thanks Matt for highlighting this.
Bottom line, please refer to the datasheet or contact us if unsure or if there's discrepancy.
Others: Since the paddle may not be tied to any specific pin. Often the designer forget to propagate this message to the PCB Layout Engineers. This is (often) easily missed and not being capture during the PCB layout stage. I find it helpful if a text note is written in the relevant schematic page/s to highlight this... to remind oneself and the Layout Engineers (just-in-case).
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