I'm working on a SHARC 21489 design. Sometimes, I work disconnected from the target processor and other times I'm connected to the target processor. I currently have Silicon Revision in VDSP set to "Automatic". What appears to happen is that the silicon revision is different when I'm connected and disconnected from the processor. Thus, my entire project group has to rebuild every time I connect or disconnect to the target processor.
I'm tempted to set silicon revision to "any" but was wondering if there is a downside in terms of performance / stability of the code?
Also, is there a VDSP listing that shows which work arounds are provided for each processor and silicon revision?