I am using the AD9381 as an evaluation front end device for a deinterlacer I run on a FPGA.
The video input is YUV 480i from a DVD, transmitted over HDMI.
I set the AD9381 control register 0x25 = 0x76:
[7:6] = 01 - 1x pixel clock.
[5:4] = 11 - high output drive strength.
[3:2] = 01 - 4:2:2 YCbCr.
 = 1 - primary output enable.
 = 0 - secondart output enable.
I expect to see pin 84 (OEF) indicating active field, but its output is always low during the whole frames. I thus conclude that the output is not interlaced, but progressive.
What's the correct setup for interlaced outptu?