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ADUC847 - Does timer 0 divide core clock by 12?

Question asked by ELADI on Jan 12, 2011
Latest reply on Jan 17, 2011 by MMA


Does the ADUC847  divide timer 0 core by 12?

 

If timer 0 core clock frequency is 12.5MHz  then the 9usec period observed seems unreasonably slow.
Why am I unable to realize a 1us interrupt cycle using timer0?

Below are the conditions of the test.
(Results from the ADUC847 quick start board)

#include <ADuC847.h>                           /* special function register declarations */

void       HundredUsDelay(int);
bit         usi = 0;

void main(void)
{
PLLCON = 0x08;
TMOD  = 0x02;              // TMOD: timer 0 , mode 2, 8-bit AUTO-reload, timer 1, mode 0 16 bit timer
TH0 = 0xff;                     // =  9 usec delay period
TL0 = 0xff;        
ET0 = 1;                        // enable timer 0 interrupt.
EA = 1;                         // enable all interupts
                                                 
while(1)
{
P0 ^= 0xFF;     
HundredUsDelay(1);
}
}

void HundredUsDelay(int count)
{
int x;

for(x = 0; x < count; x++)
{
usi = 1;                         // set flag
TR0 = 1;                        // Start Timer 0 Running
while(usi);
}          
return;
}

void timer0_ISR (void) interrupt 1
{
usi = 0;                         // stop Timer 0
TR0 = 0;                        // clear flag
}

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