Hello!

Question from customer: How to reach performance of 34.5us for 1024 Point Complex FFT using the ADSP-21479? Is there any code example or library available?

Customer's calculations (based on ADSP-214xx_HRM_rev0.3) shows that 39168 cycles (294.5us) are requred for 1024 pint FFT on signal lengths with power of 2.

Thanks,

Aleksey

Hi,

The 39168 cycles you got is using the hardware accelerators on the 21479. The algorithm used for large FFTs in the hardware accelerator requires these cycles. You could implement the FFTs in software in the core to acheive higher performance for FFTs

You can find library software codes for complex FFT (CFFTN) which are optimized for SHARC SIMD defined under filter.h as descrobed in the runtime library manual at the following link.

http://www.analog.com/static/imported-files/software_manuals/50_21k_rtl_mn_rev_1.4.pdf

You can also find the benchmark code radix 2 FFT for this at the following link. Though these benchmarks are for 21364 they are applicable to 21479 as well.

http://www.analog.com/en/embedded-processing-dsp/SHARC/products/code-examples/2136x_application_code_examples/resources/fca.html.

Thanks,

Divya