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ADAU1361 PLL lock problem.

Question asked by vvp on Jan 7, 2011
Latest reply on Jan 7, 2011 by vvp

Hi!

 

I am going to clock ADAU1361 CODEC core from its internal PLL using 12MHz external MCLK signal. I do the following:

1. Load PLL control register with 6 byte word described in the ADAU1361 Rev. C datasheet (Table 16, row 2) to lock at 45.1584MHz. This time I reset PLLEN bit to disable PLL according to the PLL initialization sequence presented in the datasheet (p. 25).

2. Load the same byte sequence to the PLL control register but set PLLEN bit to start locking.

3. Periodically poll PLL control register.

Each time I poll the PLL control register the Lock Bit equals zero i.e. PLL is not in lock. If I try to clock the core from MCLK signal directly it seems that all goes fine since I have acces to internal registers (can read their default values at least). What can be wrong with the PLL initialization?

 

Thank you in advance,

 

Vladimir.

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