I have a quick question about interrupt latching on the 21375.
Here's the scenario: I have a program that periodically checks the SPIHI bit of the IRPTL register to see if a SPI DMA transfer of eight 16-bit words has been completed (this indicates that a message has been received from the host processor).
I don't have the corresponding mask bit set, so i don't trigger a jump to an ISR for this condition, I just periodically check the SPIHI bit to see if it is time to service a message.
This is what I tried to do in my checking routine:
bit tst irptl SPIHI; //check to see if a SPI DMA transfer has completed, setting the SPIHI bit
if not TF rts; //if not, exit
bit clr irptl SPIHI; //if set, clear the latch status bit before processing the message
The problem is, if I clear the bit this way, it is no longer set to 1 when new messages are received. So clearing it like this is disabling it somehow. But I don't see what the problem is with doing it this way, can anyone enlighten me?