I would like to use 3 of the ADuC7026 DACs to generate 3 sinewaves.

The frequency of these sine waves should be up to 5kHz and be programmable with a 1Hz resulotion.

Is this possible?

I would like to use 3 of the ADuC7026 DACs to generate 3 sinewaves.

The frequency of these sine waves should be up to 5kHz and be programmable with a 1Hz resulotion.

Is this possible?

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The maximum output voltage on the DACs is 3.6V (the device supply).

Having a programmable amplitude means saving different look up tables, each of them with 256 points.

Having different frequency on each of the DAC is possible, the reload of the DAC values will have to be done by the ARM7 and not by the timer.

The timer would reload all DACs at the same time, giving the same frequency on the 3 DACs.

In this scenario all the processing power of the core is used to update the DACs.

The combination of 3 different frequencies + 3 different amplitudes + 256 points is not possible on the ADuC7026.

The number of steps in the sine wave would need to be reduced to be able to output 3 different frequencies.

You might want to try with the following algorithm, and forget about lookup tables altogether:

y(n) = y(n-1) * exp(i*wT)

where y(n) is next sample to be generated, y(n-1) is previous sample, w = 2 PI f, and T = 1 / fs, fs being the sampling frequency. All this boils down to two equations per sinewave generated:

yr(n) = yr(n-1) * cos(fi) - yi(n-1) * sin(fi)

yi(n) = yr(n-1) * sin(fi) + yi(n-1) * cos(fi)

Here fi = 2 PI f / fs (f == required frequency and fs == sampling frequency)

More on this in Richard G. Lyons: "Understanding digital signal processing" (second edition), chapter 13.32, page 576.

I have implemented it on ADUC7024 with two DACs and it works fine for me. The CPU load is almost 50% with FIQ's occuring every 10us (fs = 100kHz). The listing follows...

#include <Analogdevices/ioaduc7024.h>

#include <intrinsics.h>

int xr1 = 1000*256;

int xi1 = 0;

int xr2 = 900*256;

int xi2 = 0;__fiq __arm __ramfunc void FIQ_Handler(void) { // fiq Handler in RAM!!!!

int xr1n, xi1n, xr2n, xi2n;

long long cos1 = 15956081; // Int(Cos(f / fs * 2 * pi) * 65536# * 256 + 0.5); f = 5000, fs = 100000

long long sin1 = 5184445; // Int(Sin(f / fs * 2 * pi) * 65536# * 256 + 0.5); f = 5000, fs = 100000

long long cos2 = 15956406; // Int(Cos(f / fs * 2 * pi) * 65536# * 256 + 0.5); f = 4999, fs = 100000

long long sin2 = 5183442; // Int(Sin(f / fs * 2 * pi) * 65536# * 256 + 0.5); f = 4999, fs = 100000GP3SET = 0x00040000; // for testing the CPU load

DAC1DAT = ((xr1 + 0x80000) << 8 ) & 0xfff0000; // DAC update on FIQ

DAC0DAT = ((xr2 + 0x80000) << 8 ) & 0xfff0000; //xr1n = (xr1 * cos1 - xi1 * sin1) >> 24; // equations for first DAC

xi1n = (xr1 * sin1 + xi1 * cos1) >> 24; //

xr1 = xr1n;

xi1 = xi1n;

xr2n = (xr2 * cos2 - xi2 * sin2) >> 24; // equations for second DAC

xi2n = (xr2 * sin2 + xi2 * cos2) >> 24;

xr2 = xr2n;

xi2 = xi2n;

T1CLRI = 0;

GP3CLR = 0x00040000; // for testing the CPU load

return;

}int main (void) {

DAC1CON = 0x13; // range AVdd/AGND

DAC0CON = 0x13; // range AVdd/AGND

// DAC1 is updated with falling edge of core clock

DAC1DAT = 0x08000000; // start from midscale

DAC0DAT = 0x08000000; // start from midscale

PLLKEY1 = 0xaa;

PLLCON = 0x01; // use external crystal, use PLL

PLLKEY2 = 0x55;

POWKEY1 = 0x01;

POWCON = 0x00; // Fclk = 41.78MHz

POWKEY2 = 0xF4;

GP3DAT = 0xff000000; // Configure port 3 as output - for testing only

T1LD = 416; // T1 load register, 16 bit, FIQ every 10us

FIQEN = GP_TIMER_BIT; // Timer T1 FIQ enable

T1CON = 0xc0; // T1 control register

__enable_interrupt(); // Enable interrupts

while(1){

GP3SET = 0x00020000; // just a tick for testing purposes

GP3CLR = 0x00020000;

}}

Good luck!

Dusan

You may be able to implement a SW controlled DDS with approximately 20 output sampling points @ 5kHz. Frequency can than be controlled with a resolution better than 1 Hz. But at all this is related to what other functionality needs to be implemented with this in the whole application.