Are the timing characteristics for the ADF4350 three wire interface shown on p5 of the data sheet correct ? We have not been able to get this to work as described.
Specifically, a rsing clock edge in the middle of the data bit does not work (data setup and hold times exceed 1us, data input changing on the falling clock edge).
We have tried a falling edge in the middle of a data bit and this does successfully program the ADF4350 (data input changing on the rising clock edge) but only if we bit-bang the the interface from a microcontroller (MSP430). Using the same microcontroller SPI interface with the same timing as this does not work.
We are using the ADF4350EB2Z Rev B evaluation board, amd applying clock, data and latch signals to pins 1,3 and 5 of J6 with resistors to the USB interface removed, i.e. USB unconnected.
The evaluation board works with the evaluation software.
Any further help on offer please ?