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Setting up a fractional-divider loop with AD9956

Question asked by johnlzy on Jan 4, 2011
Latest reply on Jan 20, 2011 by johnlzy

Hi there,

 

I'm hoping someone will help me with a problem regarding the set up of the fractional-divider loop on the AD9956 evaluation board. I've purchased the AD9956-VCO/PCB-Z boards and I've been trying to set this up to no avail.

 

I've taken a look at the data sheet and noticed that they've recommended this setup (pg 16):

fig23.GIF

With the eval board, I've connected it as such:

 

DUT FILTER OUT (J6) to DUT OSC IN (J3)

VCO OUT (J16) to DUT RF_IN (J1)

VCO OUT (J16) also to split to a Spectrum Analzyer

 

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These are the settings that I've set:

 

Control

 

Clock

Ref Clock: 2400 MHz

RF Divider RefClk Mux: Unchecked

Divider Ratio: 8

System Clock: 300 MHz

RF Divider Reset Enable: Unchecked

RF Divider Reset Mode: 0

 

Accumulator Control, Power Down, SyncMulti DUT's

(All unchecked)

 

Output Waveform

Cosine

 

Linear Sweep

Enable: Checked

No Dwell: Unchecked

Load SRR @ I/O Update: Unchecked

 

Profile

Profile 0

Output Freq: 24.00000

Offset: 0.000

 

Profile 1

Output Freq: 25.00000

Offset: 0.000

 

Clock Driver Control, Phase Frequency Detector & Charge Pump

Charge Pump Full Powerdown: Unchecked

Charge Pump Quick Powerdown: Unchecked

Enable Crystal Oscillator: Checked

RSet Value: 3090

Charge Pump Current: 4.013 mA

Charge Pump Polarity: GND Reference VCO

Divider N/M : Bypass

PLL Lock Enable: PLL Lock detect

PLL Lock Mode: Lock Detect

 

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What I've observed is a static frequency at 2.315 GHz while I should be expecting a chirp frequency.

 

Thanks and Regards,

John

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