I can' find how the VGA block of EDID is maped into the EDID block of the ADV7842. I can see only the HDMI blocks
Did someone used it so far?
We will be on holiday starting Friday 12/24. We will plan to discuss with the ADV7842 experts when we return in January.
You have to set the VGA_EDID_ENABLE bit to 1 to enable use of the VGA_SCL and VGA_SDA pins for a source to access the internal EDID memory.
This is not the point.
In the HW manual paragraph 8.9 and 8.10 there is a description how the internal EDID memory is mapped to the 2 HDMI channels .If I understand correctly this 256 byte are fully used by the HDMI channels and I don't see how this memory is mapped to the VGA EDID and where is the EDID structure of the VGA channel.
There is only 1 EDID memory map available regardless of how you use it. The docs implies that enabling the internal EDID means only the lower segment of that memory is available for programming but you can put whatever you want in there.
You mentioned there is 1 EDID memory map available. Along those lines, we are trying to use one 7842 to simultaneously qualify the HDMI input and the anlog RGBHV input. The RGBHV input will come from a PC. The PC will want to read our EDID via VGA_SCL and VGA_SDA connected to the 7842 but at the same time the HDMI will need to have access to the E-EDID via the DDCS lines on port A.
Is this possible? We are trying to figure out what address is the VGA EDID going to go to and what address is the HDMI EDID going to on the 7842.
There is only 1 internal EDID memory so any DDC traffic is going to read the same data. You wouldn't be able to have different data for the VGA versus HDMI so I'm not sure it's practical to do them both simultaneously.
If it is the same data for the HDMI port and VGA though-- seems like it should be fine.
Some additional info on how to handle dual-EDIDs if they are different. It's not ADV7842, but it's the same idea.
In the software reference manual the VGA_EDID_ENABLE (0x7F) mentions “Enables I2C access to internal EDID ram for VGA port. Note that enabling this bits disables access to upper segment in DDC ports “
Would explain what that means? It seems it means that the lower segment of the internal EDID (0x00-0xFF) will only be available for HDMI and VGA EDID to see if we enable the VGA_EDID_ENABLE. If we try to have both HDMI and VGA read the same EDID.
It means exactly what you think-- the VGA DDC only can access one block of EDID. If your EDID for HDMI uses both blocks then you wouldn't be able to see it from the HDMI ports.
You could work around this by not asserting HPD until you turned VGA_EDID_ENABLE off and turning it back on when HDMI inputs go away.
A more complete answer: http://ez.analog.com/message/42271#42271
thanks so much for your help. The link to seems to indicate that the VGA_EDID_ENABLE is only set when programming the edid.
"For programming the ADV7842, the VGA_EDID_ENABLE needs to be set. VGA This switches the EDID pointer to read and write to the 128bytes from the VGA section. "
but in your reply you mentioned "You could work around this by not asserting HPD until you turned VGA_EDID_ENABLE off and turning it back on when HDMI inputs go away."
So the key is we just won't be able to simultaneously access VGA EDID and HDMI EDID. We have to pick one or the other. I think everyone thought we could have both source devices, a PC (VGA) and DVD (HDMI), read the 1 EDID on the 7842 whenever the source devices needed to read the EDID while they were both plugged in. Even if we create a shared EDID for both the HDMI and VGA sources they won't be able to access the EDID without setting and unsetting the VGA_EDID_ENABLE bit. Is that about right?
The answer I linked they do use separate sections-- top part is for HDMI and bottom for VGA and they must be separate EDIDs. They can be used simultaneously though.
The HPD think I mentioned is if you needed for that 256 bytes for the HDMI EDID only. It's not a typical case.
If you know the answer that would be good also so I can tell our folks. I asked this question on the other thread.
would you explain the line " When using the VGA and HDMI EDID the top 256bytes are used for VGA EDID and the HDMI EDID size is set to 256bytes." a little more?
In the setup you mentioned is it a completely different VGA EDID and HDMI EDID? Or, are the first 128 bytes shared between the VGA EDID and the HDMI EDID. So when the VGA source reads the EDID it reads 128 bytes max. When the HDMI EDID comes it reads 256 bytes but the first 128 bytes are the same as what the VGA read?
In total, the ADV7842 has 512 bytes available for EDID.
If not using VGA EDID, the full 512 bytes can be used for HDMI.
When VGA_EDID is enabled, the HDMI EDID is restricted to 256bytes and the VGA EDID uses the 128bytes.
The last 128bytes are not used in this configuration.
The VGA and HDMI EDIDs are not shared.
The VGA port will access the 128bytes directly, (stored in upper half of the on-board RAM) and the HDMI will access 256bytes direct (stored in lower part of RAM)
Hope this helps
your explanation is very clear. Now once we setup up the 128 bytes for vga edid and then 256 bytes for hdmi edid we can just change the hmdi edid anytime we want and the vga can have access to the edid independent of the hdmi being plugged in or not.
all this worked.
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