I am getting confused about how to configure internal SDRAM banks, as per EE-276. I have two 16-bit SDRAMs connected in parallel as 32-bits to the EBIU. Each device has 4 internal banks, and the BF561 can optimize fetches to and from different banks. How do I configure the memory declarations and LDF to keep the code in bank0, the readBuffer in bank1, and the writeBuffer in bank2?
I admit that I got mixed up by internal vs external banks.
The SDRAM devices are: MT48LC23M16 (8M x 16b x 4 banks).