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SDRAM internal bank config

Question asked by Laz on Dec 21, 2010
Latest reply on Aug 8, 2011 by Laz

I am getting confused about how to configure internal SDRAM banks, as per EE-276.  I have two 16-bit SDRAMs connected in parallel as 32-bits to the EBIU.  Each device has 4 internal banks, and the BF561 can optimize fetches to and from different banks.  How do I configure the memory declarations and LDF to keep the code in bank0, the readBuffer in bank1, and the writeBuffer in bank2?


I admit that I got mixed up by internal vs external banks.


The SDRAM devices are: MT48LC23M16 (8M x 16b x 4 banks).