I am using AD9912 in a RF synthesizer design. My 1 GHz clock is a multiplied OCXO with -140dBc/Hz phase noise at 10kHz. I am using AD9912 with PLL, HSTL and CMOS disabled and obeying all the power supply partitioning rules given in the datasheet. For 172.5MHz AD9912 output frequency, my phase noise is about -139dBc/Hz. It seems that I am hitting the phase noise floor of AD9912.
However, in the datasheet, the phase noise of 171MHz signal appears to be lower than -145dBc/Hz at 10kHz offset. Is this measurement made on the AD9912 EVAL board or on some other board. Can you give me some advice to improve the phase noise?