Is it possible to vary the period between SDA/SCL rise/fall times during I2C Start and Stop conditions?
If so - how?
The Stop condition can be delayed by writing to the I2CxCCNT registers.
This is an 8-bit counter that holds SDA low during Start/Stop conditions.
The delay counter is based on HCLK (Core clock / CD).
Each bit is 2 x HCLK.
I2C0CCNT = 0 - No delay.
I2C0CCNT = 0xFF - Maximum delay.
This is valid in Master mode only
Observations with an oscilloscope contradict this. The only effect I have seen is that a non-zero value doubles the length of the start bit.
It should work - this code worked for me:
POWKEY1 = 0x01; POWCON = 0x0; // 41.78MHz POWKEY2 = 0xF4;
GP1CON = 0x22; // I2C on P1.0 and P1.1
I2C0CFG = 0x82; // Master Enable & Enable Generation of Master Clock // I2C-Master setup I2C0DIV = 0xCFCF; //Baud = 100kHz
IRQEN = 0x400; // I2C0 Master Interupt I2C0CCNT = 0x80; // <--- Adjust this value // Transmit I2C0ADR = 0xA0; // set i2c address (LSB = 0, Master Write) I2C0MTX = 0x55; // send i2c byte address
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