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TS201 pipeline wait cycles

Question asked by Reflection on Dec 13, 2010
Latest reply on Feb 9, 2011 by Reflection

I am working with pipeline simulator now and trying to eliminating stalls, I faced this kind of issue: in the help to Visual DSP Studio it is written literally about wait (W) event: "An instruction at a stage of the pipeline waits to be executed (because of a stall down the pipeline)."
Actually I see that this is not complete true. In my case sometimes I have long chains of W-states without any stalls down the pipeline or sometimes stalls present, but they take 1 or 2 ticks, whereas W-cycles take 5 ticks and more.

Does this mean that W-cycles occure not only due to stalls (but to load from memory, for example).



Could you please clarify this issue?


Thank you in advance!