The rising edge of vsync is earlier or later than the rising edge of hsync. How to make them aligned?
Do you mean aligned to the same VCLK edge? Or they are on the same clock edge but offset less then 1 clock time from each other?
Thank you for your response.
I do not mean alignment to LLC out. I mean Vsync out should be aligned to Hsync out in progressive mode. Here Hsync can be think as clock. I found the rising edge of Vsync out is several LLC clocks later than rising edge of Hsync but in some other resolution it is several LLC clocks later than falling edge of Hsync.
I see.. positioning of the syncs is going to largely be coincident with the input synchs unless you customize it. You do have some control over this with the registers in the CP. It's described in the hardware manual in this section: 8.10 CP Output Synchronization Signal Positioning. I don't know that I've had someone try to make sure the edges of H and V are aligned so don't have any particular favored settings.
Is there something about your application that requires those edges to be aligned?
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