I will be writing an application for a SHARC 21469 chip on an Ez-Kit board with an Audio Ez-Extender, running at 48 kHz sampling rate.
I have been looking over the sample code. The sample code that I have found is only activating one of the three codec chips, to allow for 8 channels out. The other two chips are being set up with a "PLL_PWR_DWN" flag.
Is there any sample code available that shows how to set up the codec chips for more than just 8 output channels? I should be able to figure out how to enable multiple codec chips if I have to, but if there is sample code that shows how to do it, that's much easier. I'd prefer to avoid re-inventing the wheel if there is a wheel diagram lying about for me to look at.
Also, looking at the block diagrams for the EZ-Extender audio board, it appears that there is a single master clock for all three codec chips. So, I believe I don't need to do any special setup to get them to keep the chips in synch; if I write blocks of audio samples to multiple codec chips, they should be output simultaneously. Is this correct?
Thanks in advance.