We uses the Aduc7028 for quite long time, and recently we encounter an issue with the ADC, after some debugging and testing, we think the cause most possibly lies in the Aduc chip design. Here's the details:
After ADC conversion complete, the ADCSTA will change from 0 to 1, if I read the ADCDAT IMMEDIATELY after the ADCSTA change from 0 to 1, sometimes I will get wrong data; However if I wait for 6 CPU clocks, I can always get the correct data.
Here's our function on the ADC conversion:
unsigned short adc_read(unsigned char channel)
Unsigned short data;
ADCCP = channel; //select the channel (0~7) for ADC conversion;
ADCCON = 0x04A3; //Single end, start conversion, ADCbusy disabled
ADCCON = 0x0423; //Single end, stop conversion,
While (!ADCSTA) ; //wait till conversion finish
data = ADCDAT >> 16;
If you want to reproduce this issue, you need to make sure the ADCDAT is read immediately after ADCSTA changing from 0 to 1. The best and easy way to ensure that is to write assembly code, because if you compile the C code to assembly, some instructions may be added between the ADCSTA waiting and the ADCDAT reading. You can use the C compiler but need to enable the optimization to high for speed, and after compile, please check the corresponding assembly code to make sure there is no instructions between ADCSTA waiting and ADCDAT reading.
May you please confirm whether our finding is the expected behavior from the point of the ASIC design? And let us know the reason that the 6 clocks of waiting is required.
Thanks very much,