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ADV7181C : PLL unlock problems with genlock

Question asked by CRU on May 7, 2015
Latest reply on May 29, 2015 by GuenterL



I'm using an ADV7181C on a PAL source in RGB mode. There wasn't any problem until my customer activates a genlock function on his video source.

What I see is :

- the first line in the vertical synchro area of each field is about 64.5µs instead of 64µs.

- the output pixel clock takes off during the second line and comes back in the 3rd line.

- HS output doesn't appear in the 2nd line

- VS output duration is wrong.


Is there a mean to make the pll bandwith widest ?


An other idea ?