I'm using an ADV7181C on a PAL source in RGB mode. There wasn't any problem until my customer activates a genlock function on his video source.
What I see is :
- the first line in the vertical synchro area of each field is about 64.5µs instead of 64µs.
- the output pixel clock takes off during the second line and comes back in the 3rd line.
- HS output doesn't appear in the 2nd line
- VS output duration is wrong.
Is there a mean to make the pll bandwith widest ?
An other idea ?