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AD9716

Question asked by Restard on May 6, 2015
Latest reply on May 7, 2015 by Restard

We are attempting to use the following circuit to produce a single ended voltage ramp on the output:

QQ截图20150507113245.png

     The circuit is based on the circuit used in the AD9716 .  The configure set as

    da_res=1,

    da_cs=0,

    da_sdio=1,

    da_sclk=0,

    da_clko=18.432MHz,

      the output generator a sin function by xilinx fpga,and the simulation is correct.

    

The AD9102 is generating signal as follow:

 

QQ截图20150507113603.png

 

Any suggestions on what might be happening?

 

Thanks

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