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ADF4106 analog lock detect output voltage

Question asked by sss on May 6, 2015
Latest reply on May 14, 2015 by rbrennan



Our customer will evaluate the ADIsimPLL @ADF4106 with analog lock detect.


In the datasheet, I checked the comment following.

"The N-channel, open-drain, analog lock detect should be operated with an external pull-up resistor of 10 kΩ nominal.

When lock is detected, this output is high with narrow, lowgoing pulses. "


And in the AN-873,

These pulses need more aggressive filtering in order to keep the locked voltage level of ALD high. In the ALD filter

(Figure 5), Resistor R1 should be increased to slow the discharge of Capacitor C1 during the low-going pulses.

Equally, Resistor R2 can be decreased to speed the charging of C1 during the high pulses.



When we set the analog lock detect Off-Chip filtering with Resistor R1 and R2, how much range is the each resistor value,min,max?

with an external pull-up resistor of R2(10 kΩ nominal) to Vcc(3V),


R2:?kΩ~10 kΩ~?kΩ


Best Regards,