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AD9361 HDL Design Question

Question asked by 85083074@qq.com on May 6, 2015
Latest reply on May 6, 2015 by rejeesh

Hi, everyone,

     I am using AD9361 and ML605 FPGA board. And I have seen that  in  the  file axi_ad9361_dev_if.v,

if (PCORE_BUFTYPE == PCORE_VIRTEX6) begin

  (* IODELAY_GROUP = PCORE_IODELAY_GROUP *)

  IODELAYE1 #(

    .CINVCTRL_SEL ("FALSE"),

    .DELAY_SRC ("I"),

    .HIGH_PERFORMANCE_MODE ("TRUE"),

    .IDELAY_TYPE ("VAR_LOADABLE"),

    .IDELAY_VALUE (0),

    .ODELAY_TYPE ("FIXED"),

    .ODELAY_VALUE (0),

    .REFCLK_FREQUENCY (200.0),

    .SIGNAL_PATTERN ("DATA"))

  i_rx_data_idelay (

    .T (1'b1),

    .CE (1'b0),

    .INC (1'b0),

    .CLKIN (1'b0),

    .DATAIN (1'b0),

    .ODATAIN (1'b0),

    .CINVCTRL (1'b0),

    .C (delay_clk),

    .IDATAIN (rx_data_ibuf_s[l_inst]),

    .DATAOUT (rx_data_idelay_s[l_inst]),

    .RST (delay_ld[l_inst]),

    .CNTVALUEIN (delay_wdata),

    .CNTVALUEOUT (delay_rdata_s[l_inst]));

  end

 

     I want  to  know what is the defination of  i_rx_data_idelay  and if I do not use the delay primitive , can the device work properly?

 

yours,

     Wang Zhi.

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