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JESD204B Subclass 1 : Link initialization

Question asked by SCO on May 6, 2015
Latest reply on May 13, 2015 by CsomI



I use an AD-FMCADC2-EBZ and a Xilinx Kintex-7 FPGA.

I generate an 8 lanes JESD204B core (v6.0 Rev1) with VIVADO 2014.4


When I look at outputs of my transceiver (FPGA fabric side). I see K28.5 (0xBC + Char is K-character) on all lanes most of the time.


But if I trig my logic analyzer to look at data when it is different from K28.5, I see that all 8 lanes regularly stopped to transmit K28.5 to send invalid data (look at rxNOTinTABLE signal)


Moreover sync never goes high at any time.




If I force Sync to be high

All lanes received garbage data



Do you have an idea of what is wrong. Or could you suggest me some verifications somewhere.


Thanks in advance for your help.