Hello learned folks,
Setup: Zedboard + FMCOMMS1, no-OS drivers
What I'm trying to do: store ADC data in DDR, and then periodically transfer it to SD card via PS SDIO
Rejeesh has said in one of those threads that the pcore (axi_AD9643_dma) can only stream in bursts of 64K (bytes?).
1) Is this the 'size' parameter in adc_capture(fmcSel, 1024, DDR_BASEADDR) ?
2) Why is it 64K? All I can tell is the size is a 23 bit value, and I don't see it being broken up in the IP core to only use 16 bits.
3) Does this mean that there is a fifo internal to the DMA controller that can store only upto 64 kbytes? And therefore is this the max 'burst' size that can be thrown over to the DDR?
4) Seems like the adc core however is continuously streaming data into the DMA core. So is the currently data simply being flushed out/overwritten in the DDR?
5) Since the adc_capture() is called in a while(1) loop in the reference design, i'm guessing we are simply writing+overwriting 1024 bytes of data in the DDR (since the base address pointer to the DDR remains the same), is my understanding correct here?
Really appreciate your help guys
Found another discussion that talks about DAC DMAC being in cyclic mode. So I assume I can do the same setup (DMAC for the ADC in cyclic mode by writing 1 to the 0x40c register?
-If I trace the cyclic mode flag into the DMA block in vivado, I can see that this basically disables 'start of transfer' and 'End of Transfer' flags.
- Since these flags are checked in the adc_capture() routine am I correct in then disabling this check statement? This should allow me to keep transfering 'size' amount of data. Question still remains, can this size then be max value i.e. 0x7f_ffff (23 bit field).
-Lastly, is this approach (i.e. setting the ADC DMA controller in cyclic mode) better than simply calling adc_capture() multiple times to continue storing data?
Message was edited by: Omkar Pradhan Time of edit: 5.25 pm on 5/5/2015