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Question asked by SCO on May 5, 2015
Latest reply on May 6, 2015 by SCO


I'm trying to make AD-FMCADC2-EBZ work, but I'm facing problem in getting DIV_CLK clock.


According to documentation, AD9625 should generate a DIV_CLK clock at ADC frequency/4.

I made a firmware to check presence of this clock on GBT_CLK_0_M2C. It works with other FMC we have but not with AD-FMCADC2-EBZ.

I checked with an oscilloscope and a passive probe (~600MHz of bandwidth ....) and it seems no clock is present on C95 or C96 capacitors.

However, 2.5GHZ clock from Crystal is ok (Seen using an 50Ohm SMA with 6GHz bandwidth oscilloscope) and PLL inside AD9625 is locked according to SPI register.

I don't understand why I cannot get DIV_CLK with my FPGA ...

Could I have some help ?

Thanks in advance.