I have a question about how to implement a JESD204 link.
It seems there is no mechanism for clock compensation when using JESD links.
So i guess it is mandatory to use a common reference clock between JESD transmiter and receiver. Am 'I right ?
If I'm right, so I guess that DIV_CLK clock from AD9625 is provided for this purpose, isn't it ?
Thanks in advance for your help.