I've read through a number of threads (and wiki) related to this issue but still unsure why I am getting ad9361_dig_tune: Tuning TX FAILED! (in both single and dual channel mode) and ad9361_dig_tune: Tuning RX FAILED (in single channel mode). I am using the Zedboard and Vivado 2014.2.
Basically, I noticed this failure when I recently upgraded my No-OS driver & the HDL AD9361 component in my own custom design (about a week ago).
By investigating this further, I decided to test a fresh new build of your HDL reference design/No-OS driver. With your latest HDL reference design and No-OS driver code, I don't see this issue!!
So I decided to reduce the number of HDL components in the system until I started to see the issue. The point at which I start to see the failure is when I am just left with the AD9361 component with all unconnected inputs tied low - except for dac_sync_in which is left floating as per the unmodified reference) . With a little further investigation, I found that the issue is present when the ADC/DAC DMA and Unpack/Pack components are removed.
I wondered if something in the HDL was being synthesized out. With the ADC/DAC DMA and Unpack/Pack components removed, I connected simple FIFO's between the ADC and DAC dma data ports of the AD9361 block, and connected up the valid signals for read/write control. I re-tested with this build and but I still get the failures.
The big question is - does the ad9361_dig_tune() function in the No-OS driver use either or both ADC and DAC dma functions in HDL? If not, what else could it be?
Note: the only init parameter I have changed is two_rx_two_tx_mode_enable to try single and dual channel modes.