Currently i wana use the vivado2014.2 to build a DDS with AD9361,but i met some problem when i read the AD9361 code ,is there any
detial expantation for the code ?
My advice would be to study the way we implemented the DDS and update our module with your code.
I don't know your degree of expertize with Verilog / Vivado IPs. If you want to make an IP which generates data and feeds it to the AD9361 to be transmitted on the DAC side, you should study ADI Reference Designs HDL User Guide [Analog Devices Wiki] , follow some xilinx tutorials on how to create an IP and interface it to the dac interface of AD9361.
There is no detailed explanation of the verilog code in respect with DDS generation. The sine is approximated as a polynomial function.
You can check in library/common/ ad_dds, ad_dds_1 and ad_dds_sine, the code related to dds generation which we implement in our design for AD9361.
Thanks for your advice.If i want to build a DDS with AD9361,and i want to add DDS to fmcomms2/zed project,when i add DDS IP,how to write my verilog code in top module file ,i strongly get confused.Is there any advices?
When i read the library/ad9361 files,such as axi_ad9361_rx.v,some interface that i can find them on ADI Reference Designs HDL User Guide [Analog Devices Wiki] and know how to use them,but some i just cna find,such as :
what does that mean?
The names are (at least to us) self explanatory-- what is your concern?
I'd like to create a 2x2 MIMO HIL using the Zed + AD-FMCOMMS3-EBZ board+AD9361+vivado 2014.2.So i have to know what are the usage of the interface sothat i can add my Verilog HDL code to the project.
Those signals are used for the AXI interface.
I'd like to create a 2x2 MIMO HIL using the Zed + AD-FMCOMMS3-EBZ board+AD9361+vivado 2014.2.So what i to do is create my own ip,and connect with tx_data_out_p[5:0] ,tx_data_out_n[5:0] interface?Can i add synchronized algorithm to the ip i create?
The easiest thing to do would be to connect your synchronized data (part of your IP) to the dac_data inputs (make sure follow dac interface requirements http://wiki.analog.com/resources/fpga/docs/hdl#dac_interface ) of the AD9361 core and program the software as you would stream data from the DDR.
You don't need to work directly with the hardware interface to the AD9361 chip.
"When the data is transmitted and received by real-world hardware, like AD9361 , it is difficult to observe the clear constellation without proper synchronization techniques. However, even with the basic settings, you are still expected to observe the transmit and receive spectrum, which is similar to the following:"on tte web:
The message:"When the data is transmitted and received by real-world hardware, like AD9361 , it is difficult to observe the clear constellation without proper synchronization techniques. However, even with the basic settings, you are still expected to observe the transmit and receive spectrum, which is similar to the following:"
on tte web:
Is there any reference sychronization technologies your cmpany offer to the users?
Our team does not provide any reference synchronization technologies. In our libiio models, we use the existing blocks from MathWorks. You can check it out the example from here:
On the receiver side, there are the following blocks used for synchronization purpose:
A coarse frequency compensation block
A fine frequency compensation block
A timing recovery block
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