I am working with the fmcommms2 and zedboard under Vivado 2014.2. the project is from https://github.com/analogdevicesinc/hdl/tree/hdl_2014_r2
I have built the project ,now I want to use the FPGA to process the data received from the ad9361, first I must get the I、Q data . I want to use the data adc_data_i0、adc_data_q0、adc_data_i1、adc_data_q1 ,they are ad9361 output ports ,their data widths is 16 bits. but from the AD9361 interface spec file,we know that the I、Q data widths is 12bits. The I and Q samples are separated with I data on P0_D[11:0] and Q data on P1_D[11:0] as show below,
I don't know the mapping relationship between R1_i[11:0] and adc_data_i0[16:0].how to get the I and Q data?