Hello to all,
the datasheet of the AD9512 do not specify a minimum slew rate requirement for the clock inputs. But unfortunately the circuit on my bench shows a dramatic increase in jitter (about 15ns absolute @ 500ns period length) when the input slew rate of the sine wave input connected to CLK1 comes down to about 10V/us (2MHz @ 0dBm). This circuit ( 12000:1 low jitter divider using three AD9512 daisy chained) is designed to be used at about 160MHz and there it works perfect. Down to 25MHz there is no issue, down to 5MHz the jitter becomes visible on an oscilloscope. The clock signal is feed to the input(s) by a balanced transformer as recommended for best performance.