Hello, After power up and before giving the first output serial sampled data, what is the shape of FCO? Is it stable clock as if the device is giving output frames or is it logical low? Thanks.
I believe there is a SPI module instantiated at the top level; it is called "spi_write_8b.v". I believe this is only used for selecting channels on the Virtex4 so you might not need this.
Our FPGA designer thinks that the only module that will be helpful to you if you are using an Artix FPGA is the "capture.v" module. Even after porting this to Artix, you would still need to design the connection to the ADC outputs, and design the FPGA to process the data according to your need.
Unfortunately, it seems that there is a lot of custom work required anytime a different FPGA capture solution is needed.
I hope your project is going well. Is this question related to capturing AD9287 data with your Artix FPGA? If so, has the sample FPGA code discussed in another EngineerZone thread helped?
If you still need the AD9287 FCO data, we can work on getting it, but if it is no longer needed, we will not worry about it.
First of all, special thanks for your close interest.
Yes , it was related to AD9287. I had a chance to look at the code that you sent but I could not figure out why SPI_control module is not included to top module. Because I did not write the code, I could not add it to top module.
In short, I could not get the data from AD9287 to my Artix 7 -xc7a200t-2fbg484i device.
Retrieving data ...