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Dual AD9361 Synchronization

Question asked by jlavie on May 1, 2015
Latest reply on Sep 1, 2016 by sripad

If I use two identical axi_ad9361 IP cores in a Zynq design and I connect the l_clk output of the master core to the clk input of the slave core, do both cores become synchronized so that I can used just single master clock for all ADC and DAC IQ transfer signals to and from both cores?


Or do I have to use the l_clk from each individual core for transfer of ADC and DAC data to and from each individual core?