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Dual AD9361 Vivado Build Error

Question asked by jlavie on May 1, 2015
Latest reply on May 14, 2015 by DEV$

I am building a Zynq design that uses 2 instances of the axi_ad9361 IP core. I get two error messages in the placer phase when I build the design on Vivado 2014.4.

 

The error messages are:

[Drc 23-20] Rule violation (PLIDC-3) IDELAYCTRL DRC Checks - IDELAYCTRL instances 'top_i/axi_ad9361_0/inst/i_dev_if/i_rx_frame/i_delay_ctrl' and 'top_i/axi_ad9361_1/inst/i_dev_if/i_rx_frame/i_delay_ctrl' have same IODELAY_GROUP 'dev_if_delay_group' but their REFCLK signals are different

 

[Drc 23-20] Rule violation (PLIDC-3) IDELAYCTRL DRC Checks - IDELAYCTRL instances 'top_i/axi_ad9361_0/inst/i_dev_if/i_rx_frame/i_delay_ctrl' and 'top_i/axi_ad9361_1/inst/i_dev_if/i_rx_frame/i_delay_ctrl' have same IODELAY_GROUP 'dev_if_delay_group' but their RST signals are different

 

I connected the same AXI-lite ACLK, the same AXI ARESET, and the same DELAY_CLK to both cores. The AXI clock and the delay clock are the same 200MHz global clock signal.

 

Did anyone else get this build error when using two cores? If so, how did you fix it? If not, how did you connect the delay clocks to the cores to avoid it?

 

Thanks in advance for your help!

John

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