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Question about AD9852 pulsed FM generation

Question asked by tmig on Apr 30, 2015
Latest reply on Apr 30, 2015 by KennyG

The data sheet on page 24 has the following (the italics and bold are mine) :


"Alternatively, the CLR ACC2 control bit (Register Address 1F hex) is available to clear both the frequency accumulator (ACC1) and the phase accumulator (ACC2). When this bit is set high, the output of the phase accumulator results in 0 Hz output from the DDS. As long as this bit is set high, the frequency and phase accumulators are cleared, resulting in 0 Hz output. To return to the previous DDS operation, CLR ACC2 must be set to logic low. This bit is useful for generating pulsed FM."


This is a confusing to me. It appears to say both ACC1 and ACC2 are cleared, but it also says in the italics that to return to the previous DDS operation (only?) CLR ACC2 must be set to logic low. It does not mention rewriting ACC1 and ACC2. Does this mean the old values in ACC1 and ACC2 are automatically restored, or should it say they also need to be rewritten to resume operation? My desire is to program the chip so I get a linear ramp chirp, then a delay, then the same chirp, same delay, etc., all without processor intervention. Is that possible?