I am using three AD9625s. Are there any layout guidelines (i.e. trace length tolerances) available?
We have a couple evaluation boards for the AD9625 available.
For best layout of the analog input, please review the board layout files in these wiki:
EVALUATING THE AD9625 ANALOG-TO-DIGITAL CONVERTER [Analog Devices Wiki]
AD-FMCADC2-EBZ FMC Board [Analog Devices Wiki]
For the JESD204B outputs from AD9625, these boards are also a good reference. The lane to lane mis-match is not particularly critical due to the frame and multi-frame data alignment that is inherent within JESD204B specification. Intra-pair skew however, it still critical and should be minimized.
Retrieving data ...