AnsweredAssumed Answered

AD9129 clocking problems

Question asked by pspear on Apr 29, 2015
Latest reply on Apr 30, 2015 by danf

I have a custom board with two AD9129 DACs. The DAC clocks are driven with a AD9517-1 PLL using an external Z-Comm CRO2500 VCO. The design is very similar to the 4-DSP FMC260/126. The clock circuit is the same as shown in Fig73 of the AD9517-1 datasheet.

 

My problem is that the DACs occasionally slip phases in the 4x divided clock. I get the best results with the AD9129 register 0x30 set to 0x02 (no zero-crossing control and duty cycle correction enabled) and with the AD9517 output level set to its minimum output. In this mode the average time between phase slips is around 1000s. Between these phase slips the DACs work fine. With the maximum AD9517 output, the time between phase slips is less than a second. With the zero-crossing control enabled (and minimum AD9517 output), about 7 seconds.

 

ADIsimClk calculates the jitter should be 135fs RMS. I measure 7ps rms with a lecroy scope but I think that is mostly due to voltage noise on the scope probe. It is possible that the problem is due to board noise but I have met or exceeded recommendations for decoupling caps and ground planes.

 

I have replaced the board traces with micro-coax thinking that it may be due to an impedance missmatch. Didn't help.

 

I'm just about out of ideas. Any suggestions are welcome. All I can think is to re-do the board with a reduced distance between the DAC and PLL (currently it is ~8cm).

Outcomes