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Problem using SelectIO to integrate a Simulink core into FMCOMMS1 Vivado project

Question asked by BrianUCSD on Apr 29, 2015
Latest reply on Apr 30, 2015 by rejeesh

Hi,  I am trying to integrate into the FMCOMMS1-EBZ Vivado 2014.2 project from the Analog Devices GitHub HDL repository but I'm getting an error.



I have developed a block in Simulink that is designed to remove a DC bias from a received signal.  I have generate an IP core from this block using MATLAB's HDL Coder for Simulink.  I am attempting to insert it into the FMCOMMS1-EZB Vivado 2014.2 project for the Zed Board. Specifically, I am trying to insert it between 1) the pins coming into the Zed Board from the FMCOMMS1  board via the FMC and 2) the axi_ad9643 core.  Because the relevant signals in the Analog Devices FMCOMMS1 project I am using are differential signals, I am trying to sandwich my DC bias removal core between two SelectIO cores.  One SelectIO core converts from differential to single-ended and the other converts from single-ended back to differential, as shown in the diagram below.




As a student, and being very new to Vivado, Simulink, FMCOMMS1 and SelectIO, I am not assuming that what I am describing is without design problems, but hopefully most such design flaws are not relevant to my question.



When I attempt to synthesize the design I get the following error about which I am unable to find much of anything on the internet:


[Opt 31-1] OBUFDS i_system_wrapper/system_i/selectio_wiz_1/inst/obufds_inst O pin is not connected to a top-level port.


By top-level port, I assume it means the ports shown on either the far left (inputs) or far right (outputs) of the block design. Basically, my understanding of the error is that it's complaining that the circled pins are connected to pins on another core (the axi_ad9643) rather that output ports on the far right of the block design.




I suspect that perhaps I have configured my SelectIO core incorrectly, so I have included screenshots of those dialog tabs as well. The first one is larger to show the pins of the core.






As a follow-up question, is there a better way to integrate the single-ended nature of a Simulink-developed block with the differential-signal nature of the FMCOMMS1 design?