Tools & H/w: zedboard+ FMCOMMS1
1) Attempt to simulate the ad9122 DAC core with a simple testbench.
2) Use HDL to initialize appropriate registers following dds init sequence in xcomm_init_Tx and dds_setup from the no-OS drivers. (Basically I simply do this in the testbench by using the s_axi_awaddr and s_axi_wdata ports.
1) I'm trying to reverse engineer and design based on the ad9122 ip core. I have a good handle on address decoding & dds selection etc. What I cannot figure out is where in the software the MMCM_drp is initialized. I can see register address #defines i.e. 0x4070 (REG_DRP_CNTRL), but no call to write to this register during dds initialization.
2) So far I can see the clocks reaching the appropriate cores, but don't have a synthesized sine wave (yet). I imagine I should see the exact data at the output that is fed to the DAC on the fmcomms, right? So basically in the simulator if I change the waveform to analog for the 32-bit o/p data (positive and/or negative outs), I should see a sine wave, no?