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AD9257 LVDS Output 'Hold Time'

Question asked by EdFisher on Apr 29, 2015
Latest reply on Apr 29, 2015 by DougI

Hi.

 

We have just about to lay out LVDS pairs on our PCB, however we are looking to ensure matched timings for all 8 channels from an AD9257 Octal ADC.

 

I have found the min/max Setup time for the LVDS outputs (tsample/28 +/- 300ps), but to calculate maximum skew times and therefore length mismatch tolerances, I need the required hold time. The only value for hold time on the data sheet is for the SPI interface not the LVDS outputs.

 

Any help would be much appreciated.

 

Thanks.

Ed

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