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General questions for HDL AXI I2S + Zynq

Question asked by jawbone on Apr 28, 2015
Latest reply on Apr 29, 2015 by rgetz

Hello all,

I have used the provided axi i2s reference IP/HDL (thank you) and Linux driver (thank you) in a custom Zynq based design running Linux 3.17. The IP is configured to use PL330 dma (DMA_TYPE=1) and has two channels (NUM_CH=1). All seems fine and I have been able to play and record 2 channel audio as expected.


Now, for my two high level questions...

1) I would like to move to 8-ch (NUM_CH=4), is this mode working, IP and driver wise?


Steps I've taken thus far:

a) I have made the changes to the IP block configuration (NUM_CH=4) and see the appropriate changes to the block's GUI symbol in Vivado 2014.4.

b) Made 8 channel WAV file with audacity as a "known" input source.

c) used aplay to play a test file... (cut from from my terminal)

  aplay -c 8 -r 48000 8ch_2k_48000.wav

  Playing WAVE '8ch_2k_48000.wav' : Signed 16 bit Little Endian, Rate 48000 Hz, Channels 8

I get no errors reported, but when the I2S lines are observed with an APx I see 8 channels active but all at 500Hz. Maybe it's the way I've made the test file?

Pulse is NOT installed.


2) Are there any reference designs/links/examples that show this IP block with (DMA_TYPE=0) and are any driver mods required?


Thank you