192kHz sample rate DAC1/1835 on EZlite-21369 without external clocks

Discussion created by clown77 on Dec 4, 2010
Latest reply on Dec 6, 2010 by clown77

Hi to all,


some people seem to be interested to run the DAC1 of the codec on the EZlite-21369 with a sample rate of 192kHz without external clocks.

Here is an example code, based on an talktru from AD. The code is an DDS with 57kHz sine-wave output, the ADC of the codec runs with 96kHz, these samples are not used, the DAC1 runs with 192kHz and outputs the sine-wave.

CLK and FS for the DAC and the SPORT1 are generated by the PCGA and synchronized with the FS of the ADC. Because the CLK-divider is in bypass-mode, it is impossible to shift the falling edge of the CLK to the falling edge of the FS by the phase register (necessary for I2S-mode).

Therefore, the CLK for the DAC and SPORT1 must be inverted. This is done by the pinbuffer of DAIP20, see SRU-initialisation.

Before running the code, position 4 of SW7 must be switched OFF to disconnect the PB4 from DAIP20-pin.This causes the power-on-self-test of the board to fail. A 10k resistor between DAIP20 and GND solves this problem, but the code also runs if the POST is failing, see PB4 switch discussion.



Best Regards


Lothar Klaas