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Clock issue between fmcomms5-ebz and zc702.

Question asked by lukronos on Apr 27, 2015
Latest reply on May 11, 2015 by lukronos



I am working with a fmcomms5 with no-Os and a zc702 FPGA board under Vivado 2014.4.

I have to implement a transfer a design from the couple fmcomms3 and KC705 to my couple of boards.

For the FPGA design I started from the Analog Device example design then I deleted some useless modules for my design.  The C code is coming from the fmcomms3 code (I just need one AD3961 for the demonstration). My problem is in the xdc part of the FPGA design.


The example design says about the clock periods (in the constraint file) :


create_clock -name rx_0_clk   -period   5.00 [get_ports rx_clk_in_0_p]
#create_clock -name rx_1_clk   -period   5.00 [get_ports rx_clk_in_1_p]
create_clock -name ad9361_clk -period   5.00 [get_pins system_i/i_system_wrapper/system_i/axi_ad9361_0/clk]


But I need different periods for my design (12.5 ns for example). The problem is that the rx_data signals becomes constants when I change it in this constraint file (with the debug message "ad9361_dig_tune: Tuning TX FAILED!" in the console... Even if in my C code I set 80 MHz in the defaults parameters. When I lie to vivado in saying that the periods are 5 ns I have the right signals (and no debug message), but it causes to me some problems like timing not closed or other problems in the design.


What I miss in the parameters in order to change this and set the right working frequency?