I am trying to use the AD9361 filter design wizard to design the FIR filter to be used to configure the Tx and Rx FIR filters of FMCOMMS4. It is single transceiver (1Tx and 1Rx). I want to design FIR filter by taking input Data Rate of Tx FIR filter greater than 61.44 MHz but the filter design wizard is not taking Data Rate greater than 61.44 MHz. Why is it limited to 61.44 MHz? And how is PLL_Div related to ADC/DAC clock rate?