When i use vivado 2014.4 to build a project,that goes well with RTL Analysis,but when i click on 'run simulation',there are 3 errors as follow:
- [VRFC 10-2063] Module not found while processing module instance ["E:/62774889Receiver/Receiver/Frame_Detection/Frame_Detection/shiftramlength16width8.v":51]
- [VRFC 10-2063] Module not found while processing module instance ["E:/62774889Receiver/Receiver/Frame_Detection/Frame_Detection/width9_multiply_width8.v":55]
- [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
- What should i do to slove to solve the problem?