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Sample Rate Jitter on ADIS16448

Question asked by BrandonjNapier on Apr 23, 2015
Latest reply on Apr 23, 2015 by BrandonjNapier

I am noticing a lot of jitter on the "sample rate" when running with the internal and an external clock signal, and want to know if this is normal. 

 

To elaborate, I am running with either the internal clock, or a 1 kHz external clock signal, and I am watching the data ready line to determine rate that the data is coming out at.  I have the external clock signal, and the data ready signal going to a scope that can measure the time between 2 cycles.  I can see that my external clock signal is spot on at 1 kHz, but the data ready signal jitters between ~980 Hz and 1030 Hz.  I get a similar level of jitter when using the internal clock signal.

 

Effectively, I am seeing jitter (50 micro-sec) on Tstdr (Input sync to data ready valid transition) in Table 2/ Figure 4.

 

The datasheet says the clock accuracy is +/- 3%, which is about the level of jitter I am seeing, so you would think "whats the problem?" 

 

I am okay with 3% data output rate error when running with the internal clock, but I would expect it to be more constant from sample to sample. Not 3% jitter.  Why would one sample cycle take that much longer than the next?

 

When I am running with an external clock, I get overall (average) perfect rate, because for each clock signal (1 kHz), I get 1 data ready signal (1 kHz) (Perfect!).  But again, why would one sample cycle be that much longer/shorter than the next?  Is this normal? The data sheet does not specify a Min/Max for Tstdr (Input sync to data ready valid transition).

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