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AD9361 issue: dig_tune and PRBS with external reference clock

Question asked by jtrimble on Apr 21, 2015
Latest reply on Apr 23, 2015 by mhennerich

Hi all,


I'm having an issue where the ad9361_dig_tune() process fails and I'd like some help understanding exactly what it's doing. I understand this is related to basically recovering the symbol timing of data sent across the LVDS bus.


We've developed a customized system that combines 2 FMCOMMS5 boards on two ZC706 boards to perform 8-channel coherent sampling.  We've modified the FMCOMMS5 boards, removing the Y301 oscillator and are providing our own common 80 MHz reference clock to both FMCOMMS5 boards through J301.  We are also using an externally-generated RX LO, and have connected this to J302 on both FMCOMMS5 boards.  We have enabled use of the external RX LO by setting "adi,external-rx-lo-enable;" in the device tree for all 9361's, and we've modified the "ad9361_ext_refclk" in the clocks section to have clock-frequency = 80000000.


The Zynq PL is architected in much the same way as the example project, except that we've removed the adi "dmac" on the RX path and added some of our own downstream processing.


We've added the ability to generate synchronized SYNC_IN pulses to the 9361's on the two FMCOMMS boards synchronously on the same edge of the reference clock.  I've developed a special "distributed" version of the MCS sync routine (based on what's in fmcomms2_adv.c in the iio-oscilloscope code) that runs both Zynqs through the multichip_sync sequence, firing the SYNC_IN pulses to the 9361's at the appropriate times (instead of those being triggered in the PL).  I've observed the sync pulses on an oscilloscope and verified that they occur during precisely the same clock cycle of the 80 MHz reference clock.


However, when I do all of the above, I sometimes see erroneous data coming across the LVDS bus from the second AD9361 on each FMCOMMS5 (especially when running at higher sample rates).  I know the data is erroneous because I see errors in the data even when I switch the 9361 into the RX BIST tone mode like so:


echo "2 0 0 0" > /sys/kernel/debug/iio/iio:device1/bist_tone

echo "2 0 0 0" > /sys/kernel/debug/iio/iio:device2/bist_tone


I get the "Tuning RX FAILED / Tuning TX FAILED" messages from the ad9361.ko kernel driver when doing the last stage of the MCS.

I'd like to understand a little better how ad9361_dig_tune() works -- it seems that it's basically just turning on the PN generator in the 9361, cycling through different data/clock delay settings on the 9361 and trying to get the rx_pnmon unit in the PL to match up with the data coming across the LVDS.  Am I missing something?  Any idea why this might be failing?  Which PN sequence is supposed to be used with the AD9361 -- there seem to be many different polynomials implemented in the Verilog?