We are using an ADV7393 in SD slave timing mode 0 (embedded SAV/EAV). We are generating the VITS (Vertical Interval Test Signal) and inserting these into the VBI lines 17, 18, 330 & 331. But we are having issues with the CVBS output of line 18. There appears to be a -3dB roll off starting at about 4.5MHz which destroys the test signal. The following screen shot shows lines 17 and 18
Our HSYNC and VSYNC lines are tied to VDDIO I expected no other SD timing mode to work. But if I now enable timing mode 1 or mode 3 then I see the following
Which is the expected waveform for line 18.
So I now know the ADV7393 has the ability to pass though VBI data unmolested so the question is how can I achieve this same effect when only using timing mode 0?