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AD9958 non-documented startup issue

Question asked by Radarsign on Dec 2, 2010
Latest reply on Sep 24, 2014 by Radioman_TE39

A AD9958 is being used as a quadrature generator for radar testing. None of the modulation capabilities of this part are being used. The part did produce very nice sine waves but a recent code change caused the output to disappear.  A SPI logic probe verified that the device was receiving the proper initialization code, same code as when the part produced an output. Register values are below.


freqh = $0040
freql = $0fb9  ' 33.333Mhz for 32583hz output default
phase = $0000  ' phase in MSB 14 bits
CSR  = $c2  ' ch0=$42, ch1=$82, both=$c2
FR1a = $00  ' temp set so PLL is off
FR1b = $0000
FR2  = $0040
CFRa = $00
CFRb = $0201  ' $0300=200mV, $0200=50mV, SINE
ACRa = $00
ACRb = $13FF  ' Max amplitude


A 5us positive going pulse on IO_UPDATE at the completion of the register data load sends the values to the core.


We went back to the code change and discovered that we had terminated SYNC_IO ((SDIO_3) low as we were in 2 bit serial comm mode and we did not need to terminate a serial command early.  This should be the proper termination for this pin in such cases but this was the cause of the output not being updated. See page 31, left column, paragraph 6 of the data sheet.


Examining the prior working code we observed that SDIO_3 was high during the 5ms reset pulse and when brought low after the reset but before the DDS' chip select was brought low.  This enables the proper output signal to be generated but is not in the documentation. Terminating SDIO_3 high or low causes the output to not function. It seems to need to be high and then go low to enable proper operation.


What is the proper sequence of signals to properly bring up the device with SDIO_3, Master Reset, and IO_UPDATE? None of the timing diagrams in the data sheet seem to show this requirement of SYNC_IO needing to have a high to low transition.


A schematic is attached.


Charles Jenkins